1. Field of the Invention
The present invention relates to a solid-state image sensor and a camera in which it is included.
2. Description of the Related Art
A planarization technique called CMP (Chemical Mechanical Polishing) is used to planarize the surface of an interlayer insulating film in a solid-state image sensor. Japanese Patent Laid-Open No. 2008-098373 discloses a technique of reducing a global step serving as the level difference of the surface of an interlayer insulating film on the entire chip. More specifically, Japanese Patent Laid-Open No. 2008-098373 discloses a technique of simultaneously forming an insulating film which covers photodiodes in the pixel area and an insulating film which covers dummy gate electrodes in the peripheral circuit area and scribe lane area, and forming an interlayer insulating film on these insulating films. Dummy gate electrodes arranged in the peripheral circuit area are formed in a space where the gate electrodes and wiring lines of MOS transistors are not dense. The insulating film which is formed in the peripheral circuit area at the same time as the insulating film covering photodiodes is not formed on the gate electrodes of MOS transistors arranged in the peripheral circuit area.
In a solid-state image sensor disclosed in Japanese Patent Laid-Open No. 2008-098373, the insulating film which is formed in the peripheral circuit area at the same time as the insulating film covering photodiodes is formed neither on the gate electrodes of MOS transistors in the peripheral circuit area nor in the space where polysilicon wiring lines are not dense. Thus, the coverage of the semiconductor substrate by the protective film differs between the pixel area and the peripheral circuit area, and, though allowable, a global step may remain. This leads to a sensitivity difference between the center and periphery of the pixel area, generating shading.